1. Field of the Invention
The present invention relates to a shift register, and more particularly, to a shift register capable of turning on a feedback circuit according to a signal from a next stage shift register.
2. Description of the Prior Art
Liquid crystal displays (LCD) are flat screen display panels that use a glass base manufacturing material. It is necessary to find ways to reduce the cost of manufacturing the LCD. Driving a control circuit using a thin film transistor (TFT) technology to make the glass base of the LCD will be a future trend utilized to realize cost reduction. This is in contrast to the current method of manufacturing wherein the silicon layer for TFT LCD is deposited from silane gas to produce a polycrystalline silicon layer that is far less suitable for producing high-grade transistors.
Referring to FIG. 1 to FIG. 3. FIG. 1 illustrates a diagram of a conventional LCD 100. FIG. 2 illustrates a diagram of a gate driving circuit 120 of the LCD 100 of FIG. 1. FIG. 3 illustrates a diagram of a stage shift register 122 of the gate driving circuit 120 of FIG. 2. As illustrated in the figures, the LCD 100 includes a display array 100, and a gate driving circuit 120. The display array 100 is utilized for displaying images, and the gate driving circuit 120 is utilized for driving the display array 110. The gate driving circuit 120 includes a plurality of stage shift registers 122. The stage shift registers 122 are electrically coupled in a series and a gate signal GOUT is generated to drive the display array 110 according to a first clock signal CK and a second clock signal XCK sequentially, and the phase of the second clock signal XCK is opposite to the phase of the first clock signal CK. Regarding the connection of each stage shift register 122, the first clock signal CK and the second clock signal XCK alternately exchange information, at the same time a clock signal input end CK1 and a clock signal input end CK2 are alternately electrically coupled to the first clock signal CK and the second clock signal XCK. Each stage shift register 122 has an output end OUT, an input end IN, and a feedback end FB. Furthermore, the stage shift register 122 includes a signal generating circuit 310, a driving circuit 320, a feedback circuit 330, a control switch 332, an output switch 334, and two reset circuits 340, 350. As illustrated in FIG. 3, the signal generating circuit 310 is utilized for generating a gate signal GOUT(N) at the output end OUT of the shift register 122 according to the first clock signal CK (Please note that the second clock signal XCK can be used in place of the first clock signal CK) while the signal generating circuit 310 is being turned on. The driving circuit 320 is utilized for generating a driving signal Q(N) to control the signal generating circuit 310 according to the input signal received by the input end IN of the shift register 122. The input signal received by the input end IN of the shift register 122 is the gate signal GOUT(N−1) or a start signal (ST) outputted by a previous stage shift register. The feedback circuit 330 is utilized for transmitting a control signal to the control switch 332 and the output switch 334 while the feedback circuit 332 is being turned on. The on and off operation of the feedback circuit 332 is controlled by the second clock signal XCK (which can also be the first clock signal CK). The control switch 332 and the output switch 334 are respectively utilized for turning off the signal generating circuit 310 and resetting the gate signal GOUT(N) outputted by the output end OUT while the control switch 332 and the output switch 334 are turned on by the control signal transmitted by the feedback circuit 330 (i.e., voltage of the output end is being lowered to a predetermined low electrical potential VSS), and the control signal transmitted by the feedback circuit 330 is a gate signal GOUT(N+1) outputted by an output end of a previous stage shift register received by the feedback end FB. The reset circuits 340, 350 are utilized for alternately turning off the signal generating circuit 310 and resetting the output signal of the output end OUT according to the first clock signal CK and the second clock signal XCK.
To further explain the detailed operation of the conventional shift register 122, please refer to FIG. 4 and FIG. 3 at the same time. FIG. 4 illustrates a clock diagram of each related signal of a shift register 122 during operation. As illustrated in FIG. 4, in time T1, the input signal (which can be the gate signal GOUT(N−1) or a start signal (ST) outputted by the output end of the previous stage shift register) is being raised to a high electrical potential, hence the thin film transistor (TFT) TFT1 of the driving circuit 320 is initialized and the electrical potential of the driving signal Q(N) is raised and the signal generating circuit 310 is also initialized. However, the first clock signal CK at T1 is at low electrical potential, the gate signal GOUT(N) outputted by the output end OUT remains at low electrical potential, furthermore the control switch 332 and the output switch 334 do not operate at point N4 because the electrical potential is low (the feedback signal GOUT (N+1) of the feedback end FB is at low electrical potential), the reset circuit 340 does not operate at point N2 because electrical potential is low (the first clock signal CK is at low electrical potential), and the reset circuit 350 does not operate at point N3 because electrical potential is low (the input signal GOUT(N−1) or ST initializes TFT8 at T1).
At time T2, the input signal GOUT(N−1) or ST received by the input end IN is being lowered to low electrical potential, thus TFT1 of the driving circuit 320 is turned off, however, the signal generating circuit 310 is still turned on and the electrical potential of the driving signal Q(N) (which is the electrical potential of point N1) is raised to high electrical potential due to electric capacitance on the first clock signal CK when the first clock signal CK is raised to high electrical potential. Additionally, at this time, the gate signal GOUT(N) outputted by the output end OUT becomes high electrical potential. Furthermore, the control switch 332 and the output switch 334 do not operate at point N4 because electrical potential is low (because TFT15 is turned on by the first clock signal CK at T2), and because the second clock signal XCK is at low electrical potential the reset circuit 340 does not operate at point N3 because electrical potential is low.
At time T3, the second clock signal XCK turns on TFT14 of the feedback circuit 330 and TFT14 is raised to high electrical potential due to the feedback signal GOUT(N+1) of the feedback end FB which directly causes point N4 to be of high electrical potential. This action also results in three additional events: first, turning on the control switch 332 and the output switch 334; second, turning off the signal generating circuit 310 (point N1 is lowered to be low electrical potential); and third, lowering the gate signal GOUT(N) outputted by the output end OUT to be low electrical potential. Furthermore, because the first clock signal CK is at low electrical potential the reset circuit 340 does not operate at point N2 because electrical potential is low, however, because the second clock signal XCK is of high electrical potential the reset circuit 350 at point N3 is of high electrical potential and at the same time that TFT3, TFT6 are being turned on, the signal generating circuit 310 is being turned off, and the gate signal GOUT(N) outputted by the output end OUT is being lowered to be low electrical potential.
Within other following time, the reset circuit 340 and the reset circuit 350 will operate alternately to turn off the signal generating circuit 310 and lower the gate signal GOUT(N) outputted by the output end to be at low electrical potential until the input signal GOUT(N−1) of the input end IN or ST is again raised to be of high electrical potential. Also, a next stage shift register 122 will repeat the above-mentioned actions thereby sequentially generating the gate signal GOUT to drive the display array 10.
However, TFT14 of the feedback circuit 330 of each stage shift register 122 continuously receives the drive of the second clock signal XCK (which can also be the first clock signal CK), in the current manufacturing method. The efficiency of the TFT will be reduced due to protracted operating time. The driving electrical potential will increase while the TFT is turned on, thus long operating time can cause the shift register 122 function to stop operating and can even reduce the operation life span which can cause damage to the gate driving circuit 120.